Design of a Processor Optimized for Syntax Parsing in Video Decoders

8International audienceHeterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100MHz and we estimate the performance that could be obtained with an ASIC

Generation of Efficient High-Level Hardware Code from Dataflow Programs

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code, due to the difficulties of compiling input imperative languages into efficient hardware code. Moreover the hardware code generated by the HLS tools is usually target-dependant and at a low level of abstraction (i.e. gate-level). A generated code at a high-level of abstraction (i.e. chip-level) is better suited to the needs of systems' architects because they can understand and control all of the design processes. We propose in this paper a new approach to HLS to generate efficient, high-level hardware code from Dataflow Programs. Implementation results (from two dynamic dataflow programs) on Xilinx, Altera and Latice FPGAs and on ASIC targeting 90nm CMOS technology are also presented

A codesign synthesis from an MPEG-4 decoder dataflow description

ISBN: 978-1-4244-5309-2 - WOSInternational audienceThe elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction language called RVC CAL. This language is dataflow oriented and thus points out the concurrency and parallelism of algorithms. Moreover CAL is supported by the OpenDF simulator and by two code generators called CAL2C (software generator) and CAL2HDL (hardware generator). The MPEG expert group has recently elaborated the Reconfigurable Video Coding (RVC) standard which defines the RVC CAL language as reference for MPEG video decoder descriptions. This paper introduces the opportunities to design an innovative system involving hardware and software IPs, embedded processors and memories from a CAL model. Practical results on a FPGA are provided with a codesign solution of an MPEG4 Simple Profile (SP)

Multi-Purpose Systems: A Novel Dataflow-Based Generation and Mapping Strategy

International audienceThe Dataflow Process Networks (DPN) Model of Computation (MoC) has been used in di ferent ways to improve time-to-market for complex multi-purpose systems. The development of such systems presents mainly two problems: (1) the manual creation of the multi-purpose specialized hardware infrastructures is quite error-prone and may take a lot of time for debugging; (2) the more hardware are the details to be handled the greater the eff ort required to define an optimized components library. This paper tackles both problems, leveraging on the combination of the DPN MoC with a coarse-grained recon gurable approach to hardware design and on the exploitation of the DPN MoC for the synthesis of target-independent hardware codes. Combining two state of the art tools, namely the Multi-Dataflow Composer tool and the Open RVC-CAL Compiler, we propose a novel dataflow-based design ow that provide a considerable on-chip area saving targeting both FPGAs and ASICs

Hardware code generation from dataflow programs

International audienceThe elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of abstraction. RVC-CAL is a dataflow programming language which provides the good features in this context. An RVC-CAL dataflow program can be compiled to various target software languages (e.g. C, Java, LLVM) with the Open RVC-CAL Compiler (Orcc). In this paper, we will present a new hardware code generator that generates a high-quality portable VHDL code with hierarchical architecture from a RVC-CAL dataflow program in a matter of seconds. The paper explains the underlying principles of the hardware code generator, and presents the results obtained from an Inverse DCT described as an RVC-CAL dataflow program

Etude de l'implémentation automatisée sur plateforme matérielle (logicielle d'applications de traitement du signal)

Les travaux présentés dans cette thèse prennent place dans un contexte de demande grandissante pour des systèmes sur puce (SoCs) toujours plus performants. De nouvelles méthodes de conception telle l'Electronic System Level Design (ESLD) sont devenues indispensables pour les architectes de SoCs qui doivent intégrer toujours plus d'applications avec des contraintes fortes sur la puissance de calcul, et l'autonomie énergétique. L'ESLD est une approche innovante basée sur la programmation à haut niveau d'abstraction et la compilation de programmes vers du code cible matériel et logiciel. Dans cette thèse, l objectif est de proposer une approche à l'ELSD (à partir de programmes flot-de-données) au sein de la norme Reconfigurable Video Coding (RVC). Plus précisément, les contributions de cette thèse se situent dans la compilation de programmes flot-de-données et leurs implémentations sur des architectures matérielles, logicielles et mixtes.The research presented in this thesis takes place in a context of growing demand for embedded systems that requires executing more and more applications. New methods and tools such as the Electronic System Level Design (ELSD) are now necessary to help designers creating new applications with respects to constraints in terms of computing power and energy efficiency. The ESLD is a recent methodology which aims at helping designers. It defines an innovative development infrastructure, in which hardware and software code are generated from programs written at a high-level of abstraction. The purpose of this thesis is to provide an approach to the ESLD (starting from dataflow programs) within the RVC-standard. Specifically, this thesis makes contributions in the area of dataflow programs compilation, targeting hardware (first element of the ESLD) and software languages; and implementation on hardware, software, and mixed hardware/software technologies (second element of the ESLD).RENNES-INSA (352382210) / SudocSudocFranceF

Emotional Cities: imaginary future of ambiances explored in the Mobiance workshop

Part of topic : Projecting and manufacturing the ambiances of tomorrowInternational audienceMobiance, a mix between Mobile and Ambiance, is a research and creation process on the impacts of the uses of mobile tools on urban design. The second Mobiance workshop, held in Nantes, France, at the beginning of October 2015, focused on captors/actuators interacting in/with cities. Captors/sensors stand for connected devices, private and public ones, mobiles and fix ones, visible and invisible ones, interacting in the public space. This paper first presents the context of the workshop and the proposals produced by the participants; then it develops an analysis of these proposals and compares them to the outcomes of the first Mobiance workshop held in 2013

La crise ivoirienne, novembre-décembre 2004

Ouvrage collectif réalisé dans le cadre du Master 2 professionnel "Histoire militaire, défense et politiques de sécurité", Université Paul Valéry-UMR 5609-ESIDNational audienc

Un outil de diagnostic des potentialités environnementales des enveloppes dans le cadre d'une Opération Programmée d'Amélioration énergétique et Thermique du Bâtiment (OPATB)

Un rappel du contexte dans lequel s'est déroulé le projet de recherche est donné en introduction. Les procédures réglementaires et les modalités générales d'organisation des opérations de réhabilitation de logements sont présentées dans le chapitre suivant. Un travail bibliographique a permis ensuite de faire un état de l'art des principaux indicateurs utilisés pour mesurer les performances des enveloppes construites (indicateurs énergétiques, thermiques, acoustiques et autres), ainsi que des techniques d'intervention courantes en bâtiment ancien. Le chapitre 6 expose les spécifications et les principes de développement d'un outil de diagnostic environnemental des enveloppes dans le cadre d'une OPATB. La structure du modèle de données, les principaux choix technologiques, les méthodes d'obtention des données environnementales par simulation et par observation in situ, ainsi que les modalités d'intégration de ces données au système sont décrits. Enfin le rapport conclut sur les perspectives ouvertes par cette recherche. L'annexe donne les attendus et les résultats de l'analyse des identités sonores de trois quartiers du secteur OPATB